that 300 series low-noise matched transistor array ics that corporation; 45 sumner street; milford, massachusetts 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation. document 600041 rev 02 features ? 4 matched npn transistors o 300 typical h fe of 100 o 300a minimum h fe of 150 o 300b minimum h fe of 300 ? 4 matched pnp transistors o 320 typical h fe of 75 ? 2 matched pnp and 2 matched npn transistors o 340 pnp typical h fe of 75 o 340 npn typical h fe of 100 ? low voltage noise o 0.75 nv/ hz (pnp) o 0.8 nv/ hz (npn) ? high speed of t = 350 mhz (npn) of t = 325 mhz (pnp) ? 500 v matching between devices ? dielectrically isolated for low crosstalk and high dc isolation ? 36v v ceo applications ? low noise front ends ? microphone preamplifiers ? log/antilog amplifiers ? current sources ? current mirrors ? multipliers the that 300, 320 and 340 are large geometry, 4-transistor, monolithic npn and/or pnp arrays. they exhibit both high speed and low noise, with excellent parameter matching between transis- tors of the same gender. typical base-spreading resistance is 25 ? for the pnp devices (30 ? for the low-gain npns), so their resulting voltage noise is under 1 nv/ hz. this makes the 300 series ideally suited for low-noise amplifier input stages, log ampli- fiers, and many other applications. the four-npn transistor array is available in versions selected for h fe with minimums of 150 (300a) or 300 (300b). fabricated in a dielectrically isolated, comple- mentary bipolar process, each transistor is electri- cally insulated from the others by a layer of insulating oxide (not the reverse-biased pn junctions used in conventional arrays). as a result, they exhibit inter-device crosstalk and dc isolation similar to that of discrete transistors. the resulting low collector-to-substrate capaci tance produces a typical npn f t of 350 mhz (325 mhz for the pnps). substrate biasing is not re quired for normal opera- tion, though the substrate should be ac-grounded to optimize speed and minimize crosstalk. an eight-transistor bare-die array with similar performance characteristic s (the that 380g) is also available from that corpor ation. please contact us directly or through your local distributor for more information. military-grade temperature range packages are available fr om tt semiconductor (see www.ttsemiconductor.com for more information). description so14 340s14-u dip14 2-matched npn transistors and 2-matched pnp transistors 340p14-u so14 320s14-u dip14 4-matched pnp transistors 320p14-u so14 4-matched npn transistors, beta = 300 min. 300bs14-u so14 4-matched npn transistors, beta = 150 min. 300as14-u so14 300s14-u dip14 4-matched npn transistors, beta = 60 min. 300p14-u package configuration part number table 1. ordering information
document 600041 rev 02 page 2 of 5 that 300 series transistor array ics that corporation; 45 sumner street; milford, massachusetts 01757-1656; usa tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation. all rights reserved. npn collector-emitter voltage (bv ceo ) 36 v npn collector-base voltage (bv cbo ) 36v pnp collector-emitter voltage (bv ceo ) ?36 v pnp collector-base voltage (bv cbo ) ?36 v collector-substrate voltage (bv cs ) 100 v collector current 30 ma emitter current 30 ma operating temperature range (t op ) -40 to +85 c maximum junction temperature (t jmax ) +125 c storage temperature (t st ) -45 to +125 c absolute maximum ratin g s 2,3 specifications 1 th a t 300 13 12 q2 1 2 3 q1 4 5 6 7 q3 sub 11 10 9 8 q4 sub 14 th a t 320 13 12 q2 11 10 9 8 q4 sub 1 2 3 4 5 6 7 q1 q3 sub 14 th a t 340 13 12 q2 11 10 9 8 q4 sub 1 2 3 4 5 6 7 q1 q3 sub 14 figure 1. 300 pinout figure 2. 320 pinout figure 3. 340 pinout v ? 0.05 ? ? 0.05 ? ? 0.05 ? i c = 1 ma, i b = 100 a v ce(sat) npn collector saturation voltage ? tbd ? ? tbd ? ? 30 ? v cb = 10 v, i c = 1 ma r bb npn base spreading resistance ? 2 ? ? 2 ? ? 2 ? v cb = 0v, 10 a < i c < 10ma r be npn bulk resistance pa ? 25 ? ? 25 ? ? 25 ? v cb = 25 v i cbo npn collector-base leakage current na na 300 ? 100 1 ? ? 600 ? 200 2 ? ? 1500 ? 500 5 ? ? i c = 1 ma i c = 10 a i os npn i b 300: |i b1 -i b2 | ; |i b3 -i b4 | 340: |i b1 -i b2 | mv mv 3 ? 0.5 0.5 ? ? 3 ? 0.5 0.5 ? ? 3 ? 0.5 0.5 ? ? i c = 1 ma i c = 10 ma v os npn v be 300: |v be1 -v be2 | ; |v be3 -v be4 | 340: |v be1 -v be2 | mhz ? 350 ? ? 350 ? ? 350 ? i c = 1 ma, v cb = 10v f t npn gain-bandwidth product nv hz ? 1 ? ? 0.9 ? ? 0.8 ? v cb = 10v, i c = 1 ma, 1khz e n npn noise voltage density % ? 4 ? ? 4 ? ? 4 ? v cb = 10v, i c = 1ma h fe npn current gain matching ? ? ? ? 300 ? ? ? ? ? 150 ? ? ? 100 100 60 ? v cb = 10 v, i c = 1 ma i c = 10 a h fe npn current gain max typ min max typ min max typ min units 300b 300a 300 / 340(q1,q2) conditions symbol parameter npn electrical characteristics 2
that 300 series transistor array ics page 3 of 5 document 600041 rev 02 that corporation; 45 sumner street; milford, massachusetts 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation. all rights reserved. specifications 1 (cont?d) parameter symbol conditions min typ max units pnp current gain h fe v cb = -10 v i c = -1 ma 50 75 ? i c = -10 a ? 75 ? pnp current gain matching h fe v cb = -10 v, i c = -1 ma ? 5 ? % pnp noise voltage density e n v cb = -10 v, i c = -1 ma, 1 khz ? 0.75 ? nv hz pnp gain-bandwidth product f t i c = -1 ma, v cb = -10 v ? 325 ? mhz pnp v be v os i c = -1 ma ? 0.5 3 mv 320: |v be1 -v be2 | ; |v be3 -v be4 | i c = -10 a ? 0.5 ? mv 340: |v be1 -v be2 | pnp i b i os i c = -1 ma ? 700 1800 na 320: |i b1 -i b2 | ; |i b3 -i b4 |i c = -10 a?7?na 340: |i b1 -i b2 | pnp collector-base leakage current i cbo v cb = -25 v ? ?25 ? pa pnp bulk resistance r be v cb = 0 v, -10 a > i c > -10 ma ? 2 ? pnp base spreading resistance r bb v cb = -10 v, i c = -1 ma ? 25 ? pnp collector saturation voltage v ce(sat) i c = -1 ma, i b = -100 a ? ?0.05 ? v pnp output capacitance c ob v cb = -10 v, i e = 0 ma, 100 khz ? 3 ? pf pnp breakdown voltage bv ceo i c = -10 madc, i b = 0 -36 -40 ? v input capacitance c ebo i c = 0 ma, v eb = 0 v ? 6 ? pf pnp electrical characteristics 2 1. all specifications are subject to change without notice. 2. unless otherwise noted, t a = 25oc. 3. stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress rat ings only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this s p ecification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pf ? 5 ? ? 5 ? ? 5 ? i c = 0 ma, v eb = 0 v c ebo input capacitance v ? 40 36 ? 40 36 ? 40 36 i c = 10 adc, i b = 0 bv ceo npn breakdown voltage pf ? 3 ? ? 3 ? ? 3 ? v cb = 10v, i e = 0ma, 100khz c ob npn output capacitance max typ min max typ min max typ min units 300b 300a 300 / 340(q1,q2) conditions symbol parameter npn electrical characteristics 2 (cont?d)
the that 300, 320 and 340 are available in 14-pin pdip and 14-pin surface mount (soic) packages. package dimensions are shown below. the 300-series packages are entirely lead-free. the lead-frames are copper, plated with successive layers of nickel, palladium, and gold. this approach makes it possible to solder these devices using lead-free and lead- bearing solders. neither the lead-frames nor the plastic mold compounds used in the 300-se ries contains any hazard- ous substances as specified in the european union's directive on the restriction of the use of certain hazard- ous substances in electrical and electronic equipment 2002/95/eg of january 27, 2003. the surface-mount package is suitable for use in a 100% tin solder process. document 600041 rev 02 page 4 of 5 that 300 series transistor array ics that corporation; 45 sumner street; milford, massachusetts 01757-1656; usa tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation. all rights reserved. 0.7500.004 (19.050.10) 0.25.004 (6.350.10) 0.30 0.02 (7.62 0.5) 0.060 (1.52) 0.075 (1.91) 0.10 typ. (2.54) 0.018 (0.46) 0.1250.004 (3.180.10) typ . 1 0.010 (0.25) figure 4. dual-in-line package outline 0.050 (1.27) ty p 0.245 (6.2) max 0.157 (3.99) max 0.018 (0.46) max 0.344 (8.74) max 0.069 (1.75) max 0.010 (0.25) ma x 1 figure 5. surface-mount package outline packagin g and soldering information parameter symbol conditions typ units through-hole package see fig. 4 for dimensions 14 pin pdip thermal resistance ja dip package soldered to board 100 oc/w environmental regulation compliance complies with january 27, 2003 rohs requirements surface mount package see fig. 5 for dimensions 14 pin sop thermal resistance ja so package soldered to board 100 oc/w soldering reflow profile jedec jesd22-a113-d (250 oc) moisture sensitivity level msl above-referenced jedec soldering profile 1 environmental regulation compliance complies with rohs requirements package characteristics
that 300 series transistor array ics page 5 of 5 document 600041 rev 02 that corporation; 45 sumner street; milford, massachusetts 01757-1656; us a tel: +1 508 478 9200; fax: +1 508 478 0990; web: www.thatcorp.com copyright ? 2010, that corporation. all rights reserved. that corporation believes all the information furnished in this data sheet is accurate and reliable. however we assum e no responsibility for its use nor for any infringements of third-party intellectual property which may result from its use. life support policy that corporation ics are not designed for use in life support equipment where a malfunction of our ics might reasonably result in injury or death. customers who use or sell our ics for such life suport application do so at their own risk, and shall hold that corporation harmless from any and all claims, damages, suits, or expenses resulting from such use or sale. caution: this is an esd (electrostatic discharge) sensitive device electrostatic charges in the range of several kv can accumulate on the human body as well as test and assembly equip- ment. this device can be damaged by the currents generated by electrostatic discharge from bodies and equipment. moreover, the transistors in this device are unprotected in order to maximize performance and flexibility. accordingly, they are more sensitive to esd damage than many other ics which include protection devices at their inputs. note that all of the pins are susceptible. use esd-preventative measures when storing and handling this device. unused devices should be stored in conductive packaging. packaging should be discharged to the destination socket before the devices are removed from their packages. esd damage can occur to these devices even after they are installed in a board-level assembly. circuits should include specific and appropriate esd protection. revision history ? 1 2 3 3 4 5 -added high h fe versions models 300a and 300b with accompanying specifications and information. -revised features, applications, and description sections -revised maximum rating section -added npn breakdown voltage spec. -added pnp breakdown voltage spec. -added packaging characteristics table. -revised disclaimer text sept. 2010 2460 02 2 changed max. operating temperature from 70 c to 85 c. april 2010 2393 01 release april 2004 ? 00 page changes date eco revision that and c are registered trademarks of that corporation.
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